1. Field of the Invention
The invention relates to a tester for testing an integrated circuit comprising a single chip or a wafer having a plurality of chips formed thereon to determine whether the integrated circuit properly operates or not.
2. Description of the Related Art
In a conventional integrated circuit tester for testing a semiconductor chip or an integrated circuit formed on a wafer, an LSI tester supplies a current, clock, address and input/output data in number equal to the number of chips and input/outputs to a chip or a wafer to be tested, and evaluates outputs of that chip or a wafer by means of an evaluation circuit. Hereinbelow will be explained a memory tester for testing a memory, as an example of an LSI tester.
With reference to FIG. 1, a conventional memory tester includes a main frame 51 and a station 52 for measurement. The measurement station 52 is provided with a measurement board 53 having a plurality of receptacles to which memories 54 to be tested are inserted for measurement.
FIG. 2 is a block diagram of the memory tester illustrated in FIG. 1. The main frame 51 of the memory tester includes a central processing unit (CPU) 61 therein, and the measurement station 52 includes a plurality of driver comparators 62. Each of the memories 54 to be tested is in electrical connection with each of the driver comparators 62 through signal lines 64, 65 and 66. Each of the driver comparators 62 supplies highly accurate and high-speed clocks as RAS signals and CAS signals to the memories 54 to be tested through the signal lines 64 and 65, and receives output data through the signal line 66. Each of the driver comparators 62 also highly accurately evaluates output data transmitted from each of the memories 54 through the signal line 66.
An LSI tester has been suggested in many publications such as Japanese Unexamined Patent Public Disclosures Nos. 62-243335, 2-239641 and 2-56947 which is based on U.S. application Ser. No. 195,667 filed on May 18, 1988 and assigned to Hewlett Packard. In addition, it is also known to provide a chip or wafer to be tested with a circuit for testing in order to test an LSI.
However, since it is necessary in a conventional LSI tester to supply and receive clocks, addresses, data and so on with high accuracy and high speed in accordance with the number of chips and input/outputs of an integrated circuit to be tested, such testers are expensive. For instance, a memory tester which can test 16 16M-DRAMs of 8 bits in parallel at 100 MHz presently costs about two million dollars.